1. Field of the Invention
The present invention generally relates to MOSFET power transistors and processes for manufacturing MOSFET power transistors.
2. Prior Art
MOSFET transistors have certain characteristics which can be advantageously applied to power applications such as in power supplies, power amplifiers and the like. In particular, a MOS transistor acts as variable resistance device, and when turned on, has a relatively low resistance inversely dependent on the width of the channel of the MOSFET transistor. Consequently for power devices, the on resistance can be reduced as desired by merely increasing the channel width, though of course this also increases the semiconductor die size required for the transistor. MOSFET devices are also easily controlled, can be fabricated with relatively high breakdown voltages as required, and do not require an on current such as the base current of a junction transistor.
Further, MOSFETs are not subject to any current concentrating phenomenon, allowing the fabrication and use of MOSFET devices having a very wide channel region and/or the operation of multiple identical MOSFET transistors connected in parallel without special protection against current hogging. This is in comparison to a pn junction type device wherein the forward conduction voltage drop across the pn junction decreases with increasing temperature. Thus for a large area, high current device, the temperature across the junction may not be perfectly uniform. Accordingly, any higher temperature region will have a lower forward conduction voltage drop, resulting in the hogging of current from other areas of the pn junction in a rapidly escalating manner until there is a local overheating and failure of the junction. Thus unless special protections are provided, large area pn junctions will fail at current densities way below current densities tolerated by small area pn junctions.
Also various semiconductor packaging techniques for increasing the allowable power dissipation of semiconductor devices are known. However, for any particular packaging technique or design, there will be a limit on the power that may be dissipated in the semiconductor device without adverse affects on the semiconductor device. This limit usually is dependent on power or average power dissipated per unit area of the semiconductor device. For a power MOSFET, the current per unit of substrate area can be increased if the on resistance of the MOSFET transistor or transistors occupying that area can be reduced.
In a conventional MOS structure, source and drain regions are formed in the substrate with a channel region having an insulated gate thereover between the source and drain. Such structures are generally used in integrated circuits, though as power devices require a relatively large substrate area. Also known, however, are trench FETs. These devices are formed by etching trenches in a silicon substrate and effectively forming MOSFETs on the sides of the trenches. Such structures have the advantage of providing a greater channel width per unit of substrate area than the more conventional planar structure, thereby having substantial advantages thereover. The present invention provides a new MOSFET structure and method of fabrication, providing even substantially greater channel widths per unit of substrate area, thereby providing MOSFET structures having a lower on resistance, and thus a higher current carrying capacity per unit area than even prior art trench FETs.